The present invention relates generally to integrated circuit (IC) design, and, more particularly, to power supply management for IC memory devices.
A need for low power electronics has been driven by portable applications, packing density of ICs and conservation of energy. Particularly in portable applications, one way to reduce power consumption and enhance battery life is to shut off most of the circuits in an IC chip during a sleep mode except those that hold data for subsequent wake-up operations.
FIG. 1 is a schematic diagram illustrating a data latch 100 that preserves data during a sleep mode. The data latch 100 comprises a master and slave latch, 110 and 120, respectively, and a balloon latch 130 coupled to a storage node 115 between the master latch 110 and the slave latch 120. Both the master latch 110 and the slave latch 120 are made of low threshold (Vt) transistors for high speed operation. But a side effect of low Vt is a high leakage current. Besides, since the slave latch 120 need to drive circuits coupled to its DOUT node, its device sizes have to be large to meet its driving requirement. The low Vt and large device sizes all contribute to high leakage current in the master latch 110 and the slave latch 120. In order to reduce power consumption during a sleep mode, power supplies to them are both shut off. During this time, the data stored in node 115 has already been transferred and stored in the balloon latch 130. The balloon latch 130 is made of high Vt devices with moderate sizes, as it only needs to drive the slave latch 120. Power supply to the balloon latch 130 is always on so that the data stored in it may be preserved. Upon the IC chip entering the wake-up mode, a RESTORE signal will let the data stored in the balloon latch 130 be written back into the storage node 115. The balloon latch 130 serves as a state retention circuit for the data latch 100.
FIG. 2 is an implementation of the balloon latch 130 with two cross-coupled inverters 210 and 220 store data at a node 215. A complementary metal-oxide-semiconductor (CMOS) transmission gate 230 along with an inverter 240 controls the access to node 215. When the SAVE signal is asserted to a logic HIGH state, the transmission gate 230 will be on and data at node 115 may be written to node 215, or vice versa.
Since the SAVE and RESTORE signals are generated inside the IC chip, conventional automatic test pattern generation (ATPG) methods cannot access and invoke them, so that the conventional ATPG method cannot test the state retention circuit, i.e., the balloon latch 130. As such, what is needed are a built-in circuit and corresponding testing methodology that invoke the save and restore functions of the state retention circuit and writes in as well as reads out test patterns for testing them.